1. Field of the Invention
The invention relates to a semiconductor device, and more particularly, a wiring line layout of a chip scale (size) package (CSP) for interconnecting chip pads of a semiconductor chip and external terminals of the package.
2. Description of the Related Art
The CSP is, in size, equal to or a little larger than a chip employed, and is used as a high-density type package miniaturized in size as compared to the chip size.
Although the CSPs are roughly classified into area-type (in which terminals are arranged in a lattice on the package surface) packages represented by BGA and LGA and peripheral type (in which terminals are arranged at a periphery) packages represented by SOP, SON, QFP, and QFN, the invention relates to the area-type CSPs.
Recently, the BGA-type CSPs are widely used in which the external terminals are arranged as a solder ball.
FIG. 3 shows a conventional BGA-type CSP 1. FIG. 3A is its bottom view, FIG. 3B is its side view, and FIG. 3C is an expanded view of part A of FIG. 3A.
In the conventional BGA-type CSP 1, external terminals 14 are arranged on the surface of a semiconductor chip 15a. The conventional BGA-type CSP 1 comprises, in configuration, a wiring line board 11, a wiring line-board opening 12 provided near the periphery of the wiring line board 11, a wiring line 13 laid on the bottom of the wiring line board 11, an external terminal 14 arranged on the bottom of the wiring line board 11, a semiconductor chip 15a a little smaller in size than the wiring line board 11 and mounted, as facing downward, on the top surface of the wiring line board 11, a chip pad 16 arranged at the periphery of the semiconductor chip 15a, and a reinforcing resin 17 applied to the side surface of the semiconductor chip 15a and the periphery of the top surface of the wiring line board 11.
The conventional BGA-type CSP1 has its external terminals arranged on the semiconductor chip surface, so that, as shown in FIG. 3C, in a direction from the outside of the package to the inside, the periphery of the wiring line board 11, the periphery of the semiconductor chip 15a, the chip pad 16, and the outer-most peripheral external terminal 14 are arranged in this order. Also, in a region where the chip pad 16 is arrayed, the wiring line-board opening 12 is provided, through which the chip pad 16 is exposed on the side of the bottom of the package. In addition, the wiring line 13 is provided to interconnect the external terminal 14 and the chip pad 16, thus providing electrical conductivity between them. For this purpose, the wiring line 13 starts from the chip pad 16 and goes to the inside to reach the periphery of the wiring line-board opening 12 and then goes around over the wiring line board 11, thus reaching the external terminal 14.
With the conventional BGA-type CAP1, however, the area for laying the wiring line 11 is arranged within the chip pad 16 and so limited to the area on such an area on the wiring board 11 except the area for laying the external terminal 14. Therefore, as the semiconductor chip 15a is reduced in size, the wiring area is also reduced. With a reduced wiring area, the wiring is rendered difficult or impossible to conduct, which leads to a problem. Since the array of the external terminals 14 is specified by the domestic standards or the international standards, an extra space between the external terminals on the wiring board cannot be changed unless these standards are not changed. Therefore, the above-mentioned problem that with a decreasing size of the semiconductor chip 15a the wiring is difficult or impossible to conduct would occur not in the extra space between the external terminals but in an area between the chip pad 16 and the external terminal. If a CSP is manufactured even when wiring is difficult to conduct in this area between the chip pad 16 and the external terminal, there occurs such a problematical risk that the chip pad 16 may be damaged due to difficulty in wiring pattern designing and thermal stress loads. These problems make up an obstacle against reduction in the chip size demanded by desired improvements in the fine patterning degree, operation speed, and power dissipation of the semiconductor devices.
In view of the above, it is an object of the invention to provide a semiconductor device that is free from the difficulty in designing of the wiring pattern as well as the damage etc. of the chip pad 16 caused by the thermal stress loads applied after the connection process, to secure stable bonding and higher reliability and also easy reduction in the chip size.
A first aspect of the invention is a semiconductor device which comprises:
a semiconductor chip having an electrode at its periphery; a wiring board on which the above-mentioned semiconductor chip is bonded; an opening for exposing the wiring board partially; an external terminal arranged on the above-mentioned wiring board in such a way as to be provided opposite to the above-mentioned semiconductor chip and also inside as viewed from the above-mentioned opening; and a wiring line laid over a surface on which the external terminal of the above-mentioned wiring board is arranged, for electrically interconnecting the above-mentioned electrode and the above-mentioned external terminal,
wherein a passage of the above-mentioned wiring line is set in such a way that the above-mentioned wiring line may start from the above-mentioned external terminal and go out of the above-mentioned opening, thus reaching the above-mentioned electrode.
According to the semiconductor device of the invention, an area which is outside as viewed from the opening formed in the wiring board is also utilized as a wiring-line laying area, to obtain a sufficient extra space for wiring, thus providing such an effect that the wiring area may not be reduced due to a change in the chip size or the chip pad position.
Therefore, failures hardly occur in reducing the chip size. The semiconductor device of the invention utilizes an extra space around the opening of the required spaces on the wiring board, to lay the wiring line, thus avoiding a situation where the wiring is difficult to impossible to conduct. The difficulty of wiring can be avoided without changing the external terminal, so that the conformity in terms of the array of the external terminals can be kept to the domestic and international standards. With this, the above-mentioned configuration of the semiconductor device according to the invention makes it possible to design a nonrestrictive and stable wiring pattern. In the case of downward-facing bonding, if the distance from the periphery to the chip pad, i.e. distance for wiring therebetween, is too short, stress due to a difference in the thermal expansion coefficient of the package constituting materials is applied to the pad, which is thus liable to be damaged. According to the invention, the wiring line starts from the outer-side periphery of the peripheries of the outer-peripheral opening, to connect to the pad, thus making it possible to provide a sufficiently large distance between the opening periphery and the chip pad. Therefore, the occurrence of a failure such as damage of the chip pad is suppressed which is due to thermal stress loads applied after the connection processes are finished, thus maintaining and even improving the package reliability.